A multiprocessor system commonly consists of a plurality of interconnected processors which cooperate to perform data handling jobs. Consequently, a large number of data messages are interchanged between the processors on a regular basis. It has long been recognized that this interprocessor communication can become a bottleneck which robs the system of computing time and diminishes its capacity for handling computing jobs. Customarily, data transfers between two processors are initiated by the processor preparing to transmit a data message. The transmitting processor first requests access to a common bus interconnecting the system processors, and, after having been granted bus access, transmits the message on the bus together with the identity of the intended receiving processor. Much effort has been devoted to resolving bus access problems, and a number of technical solutions are known for handling bus access requests on a priority basis while minimizing access delays resulting from conflicting access demands. Some bus access arrangements assure "fair" access to a bus in that, while providing access on a priority basis, a low priority processor is not allowed to be excluded for an inordinately long period of time. The prior art, however, has not successfully addressed the problem of fair access to a receiving processor after access to the bus has been obtained by a message transmitting processor. A transmitting processor of a multiprocessing system, after having waited for access to the bus, may find that the receiving processor is unable to accept a data message. In prior art systems the transmitting processor must then try again to gain access to the bus and may be denied access to the receiving processor again. When this happens often, a particular processor may be prevented from performing its tasks for an inordinate length of time and potentially forever. This repeated denial of access is a burden to the system and reduces the system's data handling capacity.
It is an object of this invention to provide "fair" access to a receiving processor from the other processors of a multiprocessor system.